In a common image sensor, charge stored in a light receiving part (for example, photodiode) of a unit pixel is read as a pixel signal and analog-to-digital (A/D) converted. There is known a solid-state imaging apparatus which achieves the conversion accuracy of the A/D conversion by switching the gradient of a reference voltage (for example, see Patent Document 1).
In the configuration of Patent Document 1, by connecting two A/D conversion circuits to the same pixel array and inputting reference voltages Vref1 and Vref2 each having a different gradient to the A/D conversion circuits from two reference voltage generation units, A/D conversion is performed with two types of gradation accuracy.
However, with the configuration of Patent Document 1, because of providing the two A/D conversion circuits, the circuit area and the power consumption are twice those of a conventional configuration. Thus, there has been proposed a configuration in which one A/D conversion circuit is provided, a determination unit determines the magnitude of a pixel signal, and either of two reference voltages Vref1 and Vref2 each having a different gradient is selected based on the determination result.
However, since the comparison accuracy (offset error) in the determination unit is different from the comparison accuracy (offset error) in a comparator of the A/D conversion circuit, although, for example, the determination unit determines that the incident light is low illuminance and that the amplitude of the pixel signal is small, the comparator of the A/D conversion circuit determines that the reference voltage is outside the voltage range due to the offset error, and the output image can be damaged. Thus, the reference voltage needs to be supplied in a voltage range with a margin for the error.
In contrast, there has been proposed a configuration in which a comparator of an A/D conversion circuit is also used for comparison in a determination unit, and gradation accuracy is selected based on the comparison result (for example, see Patent Document 2).
With the configuration of Patent Document 2, it is possible to reduce the margin in the voltage range of the reference voltage due to the comparison accuracy (offset error) in the determination unit, implement acceleration of A/D conversion or power consumption reduction, and suppress generation of errors in the A/D conversion.